Programmable logic devices (PLDs) are a class of integrated circuits (ICs) which can be programmed by a user to implement a logic function. Logic designers typically use PLDs to implement logic functions in electronic systems because, unlike custom hardwired or "application specific" integrated circuits (ASICs), PLDs can be programmed in a relatively short amount of time, and often can be reprogrammed quickly to incorporate modifications to the implemented logic function.
One major class of PLDs are referred to as programmable logic array (PLA) devices or programmable array logic (PAL) devices. Basically, these early PLDs include an AND plane which ANDs two or more input signals to produce product terms (P-terms), and an OR plane which ORs two or more of the P-terms generated by the AND plane. The AND plane is typically formed as a matrix of programmable connections where each column connects to an input pin of the PLD, and each row forms a P-term element which is transmitted to the OR plane. The OR plane may be programmable (i.e., each P-term element is programmably connectable to one of several different OR plane outputs), in which case the PLD is called a PLA device. Alternatively, the OR plane may be fixed (i.e., each P-term element is assigned to a particular OR plane output), in which case the PLD is called a PAL device. The AND plane and OR plane of PLA and PAL devices implement logic functions represented in "sum-of-products" form.
PLA and PAL devices were well-received by logic designers when their implemented logic functions were relatively small. However, as logic functions grew increasingly larger and more complex, logic designers were required to wire together two or more small PLDs to provide sufficient logic capacity. Although this process was tolerated during development and testing, it increased the cost and size of production units. This generated a demand for PLDs with increasingly larger logic capacity.
To meet the ever-increasing demand for greater capacity, PLDs with increasingly complex architectures have been developed. One popular complex PLD type, known as complex programmable logic devices (CPLDs), includes two or more function blocks connected together and to input/output (I/O) modules by an interconnect matrix such that each of the function blocks selectively communicates with the I/O modules and with other function blocks of the CPLD through the interconnect matrix. Each function block of the CPLD is structured like the two-level PLDs, described above. In effect, these CPLDs incorporate several early PLDs and associated connection circuitry onto a single integrated circuit. This provides a circuit designer the convenience of implementing a complex logic function using a single IC.
Each function block of an early CPLD typically includes an AND array and a set of macrocells. The input signals of the AND array are received from the interconnect matrix. A specific number of P-term elements generated by the AND array are assigned to each macrocell. Each macrocell includes an OR gate which is programmable to receive one or more of the assigned P-term elements, and also to receive a sum-of-products term from an adjacent macrocell of the function block (see the discussion below regarding the "chaining" process). The OR gate of each macrocell produces a sum-of-products term which is either transmitted to the I/O modules of the CPLD, fed back through the interconnect matrix, or is transmitted on special lines to an adjacent macrocell.
As PLDs grow in size and complexity, the ability to adjust their performance characteristics (e.g., power consumption and signal quality/speed) is becoming more important to logic designers. For example, logic designers may require low power consumption and/or high quality output signals in some applications. In other applications, however, logic designers may be willing to sacrifice high power consumption and a reasonable amount of output signal noise for fast pin-to-pin speeds (i.e., the time required for a signal to pass from an input pin to an output pin). To address these contrasting requirements, some PLD manufacturers offer PLDs which are selectively operated in either a fast-speed, high-power mode or in a slow-speed, low-power mode. In addition, some PLDs provide adjustable slew rates which selectively reduce output noise at the expense of signal speed.
A problem with PLDs providing power and slew rate control arises when a logic designer requires high speed operation for only a portion of the implemented logic function. When this occurs, the logic designer often must run the entire PLD in the fast-speed, high power mode in order to meet the timing specifications of the small portion of the logic function. Of course, this increases power consumption of the entire PLD, even in portions of the logic function which do not require high-speed operation.